1. Field of the Invention
The present invention relates to an integrated circuit for sensing the stored information of a semiconductor Non-Volatile Memory (NVM). In particular, the present invention relates to circuitry and operating method of using a referencing memory cell to sense the information stored in a semiconductor NVM.
2. Description of the Related Art
Semiconductor Non-Volatile Memory (NVM), and particularly Electrically Erasable, Programmable Read-Only Memories (EEPROM), exhibit wide spread applicability in a range of electronic equipments from computers, to telecommunications hardware, to consumer appliances. EEPROM cells store datum by modulating their threshold voltages (device on/off voltage) of the Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) by the injection of charge carriers into the charge-storage layer above the channel regions of the MOSFETs. For example, an accumulation of electrons in the floating gate, or in a charge-trap dielectric layer, or nano-crystals above the transistor channel region, causes the MOSFET to exhibit a relatively high threshold voltage. The unique threshold voltage of the memory cell modulated by the stored charges can be applied to represent a state of information. When the power of the semiconductor memory cell is “off” the stored charges still remain in the memory cells. Therefore, the stored information for the correspondent threshold voltage in the memory cells is “non-volatile” even with the power “off”. One class of EEPROMs, Flash EEPROM, may be regarded as specifically configured EEPROMs into cell array that may be erased only on a global or sector-by-sector basis. Flash EEPROM has the advantages of higher compact density and high programming/erase speed over the conventional EEPROM. Flash EEPROM arrays have been broadly applied to mass storage of program codes and digital datum for electronic equipments.
The conventional current-sensing scheme for reading-out the EEPROM cells using a referencing semiconductor NVM cell is shown in FIG. 1, where voltage biases are applied to control gate, source electrode, substrate electrode, and one terminal of a pull-up element 130 with the other terminal attached to the drain electrode of a read EEPROM cell Mc. The current flowing through the drain electrode is then amplified by a current mirror amplifier 120. An identical circuit configuration attached with a referencing cell Mrf is also constructed. The two outputs of the pair of the symmetrical circuitries attached with a read NVM cell Mc and a referencing cell Mrf respectively are then fed into a differential voltage sense amplifier 110 for the comparison of the amplified currents. The output of the differential voltage sense amplifier 110 further pushes the voltage comparison result to a data latch buffer (not shown). The final outcome of the data latch buffer indicates that the current generated from the read NVM cell Mc with the applied voltage biases is greater than the referencing current and vice versa. In one particular case for the referencing current generated from an identical referencing NVM cell Mrf with the same applied biased to both read cell Mc and referencing cell Mrf, the outcome of the data latch buffer indicates that the threshold voltage of the read cell Mc with less cell current is higher than that of the referencing cell Mrf and vice versa. Therefore, with the same biases to the identical read and reference cells, the sensing scheme is basically to compare the cells' threshold voltages between the read cell Mc and the referencing cell Mrf. Since the mismatch between the symmetrical circuitries and memory cells from manufacturing non-uniformity causes the ambiguity of cells' threshold voltages, in practice, a cell threshold voltage guard band between the read cell and referencing cell has to take into account to separate the ambiguity. This cell threshold voltage guard band imposes a limitation on the numbers of states represented by the threshold voltages of NVM cells in the multi-bit per cell storage application.
One disadvantage for the conventional current-sense scheme is that the cell currents for both cells require being “on” and amplified by the current mirror amplifiers 120 to maintain steady state voltage potentials at the two inputs of the differential voltage sense amplifier 110. Due to the direct current paths from the pull-up elements 130 to NVM cells and, mostly from the amplified mirrored currents, the power consumption for the sense scheme is high. In practice, the high current consumption in the sensing circuitry imposes a key limitation factor of having a large number of NVM cells parallel read in semiconductor NVM circuit design.
In this invention, we have proposed a new kind of semiconductor NVM reading-out scheme using a referencing cell. The new scheme can resolve the threshold voltage difference between the read cell and the referencing cell to a very good accuracy with a proper sensing speed. In particular, the new scheme has no direct current paths in the circuitry but only the switching currents during the sensing period resulting in a small current consumption reading.